NXP Semiconductors /LPC18xx /USB1 /PORTSC1_H

Current connect status This value reflects the current state of the port and may not correspond directly to the event that caused the CSC bit to be set. This bit is 0 if PP (Port Power bit) is 0. Software clears this bit by writing a 1 to it.

0 (NO_DEVICE_IS_PRESENT): No device is present.

1 (DEVICE_IS_PRESENT_ON): Device is present on the port.

Connect status change Indicates a change has occurred in the port’s Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be setting an already-set bit (i.e., the bit will remain set). Software clears this bit by writing a one to it. This bit is 0 if PP (Port Power bit) is 0

0 (NO_CHANGE_IN_CURRENT): No change in current status.

1 (CHANGE_IN_CURRENT_ST): Change in current status.

Port enable. Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled. downstream propagation of data is blocked except for reset. This bit is 0 if PP (Port Power bit) is 0.

0 (PORT_DISABLED_): Port disabled.

1 (PORT_ENABLED_): Port enabled.

Port disable/enable change For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This bit is 0 if PP (Port Power bit) is 0,

0 (NO_CHANGE_): No change.

1 (CHANGED): Port enabled/disabled status has changed.

Over-current active This bit will automatically transition from 1 to 0 when the over-current condition is removed.

0 (THE_PORT_DOES_NOT_HA): The port does not have an over-current condition.

1 (THE_PORT_HAS_CURRENT): The port has currently an over-current condition.

Over-current change This bit gets set to one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position.

Force port resume Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed K) is driven on the port as long as this bit remains a one. This bit will remain a one until the port has switched to the high-speed idle. Writing a zero has no affect because the port controller will time the resume operation clear the bit the port control state switches to HS or FS idle. This bit is 0 if PP (Port Power bit) is 0.

0 (NO_RESUME): No resume (K-state) detected/driven on port.

1 (RESUME_DETECTED): Resume detected/driven on port.

Suspend Together with the PE (Port enabled bit), this bit describes the port states, see Table 302 Port states as described by the PE and SUSP bits in the PORTSC1 register. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. The host controller ignores a write of zero to this bit. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This bit is 0 if PP (Port Power bit) is 0.

0 (PORT_NOT_IN_SUSPEND_): Port not in suspend state

1 (PORT_IN_SUSPEND_STAT): Port in suspend state When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.

Port reset When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver. This bit is 0 if PP (Port Power bit) is 0.

0 (NOT_IN_RESET): Port is not in the reset state.

1 (PORT_IS_IN_THE_RESET): Port is in the reset state.

High-speed status

0 (NOHIGHSPEED): Host/device connected to the port is not in High-speed mode.

1 (HIGHSPEED): Host/device connected to the port is in High-speed mode.

Line status These bits reflect the current logical levels of the USB_DP and USB_DM signal lines. USB_DP corresponds to bit 11 and USB_DM to bit 10. In host mode, the use of linestate by the host controller driver is not necessary for this controller (unlike EHCI) because the controller hardware manages the connection of LS and FS.

0 (SE0): SE0 (USB_DP and USB_DM LOW)

1 (J_STATE): J-state (USB_DP HIGH and USB_DM LOW)

2 (K_STATE): K-state (USB_DP LOW and USB_DM HIGH)

3 (UNDEFINED): Undefined

Port power control Host controller requires port power control switches. This bit represents the current setting of the switch (0=off, 1=on). When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. When an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller driver from a one to a zero (removing power from the port).

0 (PORT_POWER_OFF_): Port power off.

1 (PORT_POWER_ON_): Port power on.

Reserved

Port indicator control Writing to this field controls the value of the pins USB1_IND1 and USB1_IND0.

0 (OFF): Port indicators are off.

1 (AMBER): Amber

2 (GREEN): Green

3 (UNDEFINED): Undefined

Port test control Any value other than 0000 indicates that the port is operating in test mode. The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification. Writing the PTC field to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into the connected and enabled state at the selected speed. Writing the PTC field back to TEST_MODE_DISABLE will allow the port state machines to progress normally from that point. Values 0x8 to 0xF are reserved.

0 (TEST_MODE_DISABLE): TEST_MODE_DISABLE

1 (J_STATE): J_STATE

2 (K_STATE): K_STATE

3 (SE0_NAK): SE0 (host)/NAK (device)

4 (PACKET): Packet

5 (FORCE_ENABLE_HS): FORCE_ENABLE_HS

6 (FORCE_ENABLE_FS): FORCE_ENABLE_FS

7 (FORCE_ENABLE_LS): FORCE_ENABLE_LS

Wake on connect enable (WKCNNT_E) This bit is 0 if PP (Port Power bit) is 0

0 (DISABLES_THE_PORT_TO): Disables the port to wake up on device connects.

1 (ENABLE_DEVICE_CON): Writing this bit to a one enables the port to be sensitive to device connects as wake-up events.

Wake on disconnect enable (WKDSCNNT_E) This bit is 0 if PP (Port Power bit) is 0.

0 (DISABLES_THE_PORT_TO): Disables the port to wake up on device disconnects.

1 (ENABLE_DEVICE_CON): Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events.

Wake on over-current enable (WKOC_E)

0 (DISABLES_OVERCURRENT): Disables the port to wake up on over-current events.

1 (ENABLE_OVERCURRENT): Writing a one to this bit enabled the port to be sensitive to over-current conditions as wake-up events.

PHY low power suspend - clock disable (PLPSCD) In host mode, the PHY can be put into Low Power Suspend - Clock Disable when the downstream device has been put into suspend mode or when no downstream device is connected. Low power suspend is completely under the control of software.

0 (ENABLE_PHY_CLK): Writing a 0 enables the PHY clock. Reading a 0 indicates the status of the PHY clock (enabled).

1 (DISABLE_PHY_CLK): Writing a 1 disables the PHY clock. Reading a 1 indicates the status of the PHY clock (disabled).

Port force full speed connect

0 (ANYSPEED): Port connects at any speed.

1 (FULLSPEED): Writing this bit to a 1 will force the port to only connect at Full Speed. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device.

Reserved

Port speed This register field indicates the speed at which the port is operating. For HS mode operation in the host controller and HS/FS operation in the device controller the port routing steers data to the Protocol engine. For FS and LS mode operation in the host controller, the port routing steers data to the Protocol Engine w/ Embedded Transaction Translator.

0 (FULL_SPEED): Full-speed

1 (LOW_SPEED): Low-speed

2 (HIGH_SPEED): High-speed

Reserved

Parallel transceiver select. All other values are reserved.

2 (ULPI): ULPI

3 (SERIAL): Serial/ 1.1 PHY (Full-speed only)